The present invention pertains generally to flip-chip bonding, and more particularly to a mechanically compliant bump for use in flip-chip bonding.
xe2x80x9cFlip-chipxe2x80x9d and xe2x80x9cflip-chip bondingxe2x80x9d refer to an assembly and method wherein a chip is attached to a substrate, which is typically another chip or a circuit board, such that chip surface (the active area or I/O side) faces the substrate. See, generally, J. H. Lau, Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies (McGraw-Hill, (copyright)2000).
Flip-chip bonding addresses two broad classes of problems. One pertains to traditional electronic packaging issues (hereinafter xe2x80x9cpackaging applications,xe2x80x9d) such as how to increase packaging efficiency (e.g., cost considerations, performance considerations, etc.). The second pertains to how to integrate two dissimilar electronic devices, such as a photonics device to a silicon-electronics chip, to form a functionally unified device (hereinafter xe2x80x9cchip-on-chip applicationsxe2x80x9d).
For packaging applications, the two electronics parts being bonded together are usually a semiconductor chip and a circuit board. Compared to the alternativexe2x80x94face-up wire bonding technologyxe2x80x94the application of flip-chip technology to electronics packaging provides higher packaging density (e.g., more input/output), potentially shorter leads, lower inductance, better noise control, smaller device footprints, a lower packaging profile and is well suited for use with area array technology.
A variety of interconnect materials and methods can be used in flip-chip bonding, including, for example, tape automated bonding, wire interconnects, isotropic and anisotropic conductive adhesives, bumps, and pressure contacts. Bumps are becoming the interconnection method of choice for a number of applications.
For packaging applications, the flip-chip bonding process with bumps comprises, in pertinent part, depositing a bump of metal on each of a plurality of contact pads that are disposed on the surface of the parts (more properly, on the surface of a wafer at this stage of the method). This step, referred to as xe2x80x9cwafer bumping,xe2x80x9d is performed using any of a variety of known techniques, including evaporation, electroplating, stencil printing and jet printing, to name a few. After deposition, the bump is heated to its melting temperature in a step called xe2x80x9creflow.xe2x80x9d During reflow, the bump assumes a semi-spherical shape due to the surface tension of the metal. In a so-called xe2x80x9ctackingxe2x80x9d operation, the bumps on the two parts are aligned and then pressed together forming an assemblage of the two parts.
Even though tacking is performed below the melting point of the bumps, bonding does occur. But to assure electrical connection in a large percentage of the bonds, further processing is desirable. To that end, after tacking, the assemblage is heated to the melting temperature of the bumps. As the bumps melt in a second reflow step, they co-mingle or weld, forming sound electrical connections in high yield.
The bumps for packaging applications are relatively large (c.a., about 100 microns) because of limitations pertaining to forming reflowed bumps. Bump pitch (i.e., spacing between the bumps) is similarly large since reflow might otherwise cause bridging (i.e., flow of metal) between adjacent bumps.
For xe2x80x9cchip-on-chipxe2x80x9d applications, flip-chip bonding with bumps provides the only commercially practical solution, at least in some cases. For example, it is very inconvenient, using wire bonding, to integrate two-dimensional arrays of devices (e.g, a focal plane array chip containing detectors) to a silicon-electronics chip containing, for example, electronic read-out, driver and/or processing circuitry. The bump and bump pitch are typically much smaller (c.a., 10-20 microns) for chip-on-chip applications than for packaging applications to allow for maximum device density and maximum I/O, as is often necessary.
Typically, a photolithographic lift-off technique is used to form bumps for both packaging and chip-on-chip applications. This technique, well known in the art, is described briefly below in conjunction with FIGS. 1-3.
FIG. 1 depicts, via a cross-sectional view, wafer 100 with resist 104 deposited thereon. In this illustration, resist 104 has already been patterned to define a plurality of openings 106 that extend from resist upper surface 108 through to wafer surface 102. Metal is deposited through opening 106 on surface 102 to form bumps 210, as shown in FIG. 2. Metal also deposits on resist upper surface 108.
Opening 106 are wider near wafer surface 102 than at resist upper surface 108, thereby creating tapered side-walls 212. Tapering the side-walls in this fashion prevents metal from coating them. The prior art teaches that side-walls 212 must be substantially metal-free to allow resist-removing solvent to penetrate to wafer surface 102 via gap 214. FIG. 3 depicts wafer 100 with resist 104 (and the overlying metal) removed leaving bumps 210.
Any type (e.g., composition, size, etc.) of metal bump can be formed using this technique, given sufficient consideration of the adhesion of the metal to the wafer. For chip-on-chip applications, a soft metal or low-temperature metal is typically used. For the purposes of this specification, the phrases xe2x80x9csoft metalxe2x80x9d and xe2x80x9clow-temperature metalxe2x80x9d mean metal(s) or metal alloys having a melting point less than about 400 xc2x0 C. Illustrative low temperature metals include, without limitation, indium compositions, and certain alloys of tin, bismuth and zinc.
There are several reasons why soft metals are used for chip-on-chip applications. First, the small bump size and pitch characteristic of chip-on-chip applications increase the likelihood that bridging might occur between adjacent bumps during reflow. Consequently, following tacking, the temperature is not raised to the melting point of the bumps. As such, all bonding occurs during tacking at sub-melting point temperatures. This sub-melting point bonding operation is referred to as thermo-compression bonding. Since temperatures are below the melting point of the bumps, thermo-compression bonding produces a relatively weak bond. The bumps used for chip-on-chip applications therefore comprise a low temperature metal to effect the best bond possible under low temperature conditions.
Second, in chip-on-chip applications, the two chips being joined typically comprise dissimilar materials having different coefficients of thermal expansion. To avoid excessive thermal stresses upon cooling that might result in bond breakage, the tacking operation is performed at relatively low temperature (less than 100xc2x0 C.). So, again, given such temperature limitations, low temperature metals will effect the best bonds.
And there is a third reason why low melting point metals are traditionally used for flip-chip bonding. In particular, it is very difficult to bring two chips (or a chip and a circuit board) together in perfectly parallel relation for bonding. Consequently, for both packaging and chip-on-chip applications, the bumps must be mechanically compliant (i.e., deformable) to accommodate the greater pressures exerted on some of the bumps when two parts are brought together out of parallel alignment.
Table I depicts a yield plot of a chip containing 256 photodetectors that are bonded to a silicon electronics chip (a chip-to-chip application) using high-temperature metal (in this case, gold) bumps. For the purposes of this specification, a xe2x80x9chigh-temperature metalxe2x80x9d means metal(s) and metal alloys having a melting point above about 400xc2x0 C. Illustrative high-temperature metals include, without limitation, gold, silver and chromium. In Table I, an xe2x80x9cxxe2x80x9d signifies no electrical connection, indicating a defective bump-to-bump bond, and xe2x80x9ccxe2x80x9d signifies a sound electrical connection.
Referring to Table I, most of the bonds located on one side of the chip (appearing at the right side of Table I) are defective. These failures occurred, in large part, due to the inability of the high-temperature metal bumps to sufficiently deform when exposed to localized high pressure resulting from the non-parallel chip surfaces.
These considerations have prompted, if not dictated, the use of low-temperature metals for chip-on-chip applications. But the use of low-temperature metals is problematic. Specifically, if the assembled chips are operated or stored at elevated temperatures (i.e., at or above 100xc2x0 C.), partial reflow of low-temperature metal bumps might occur, causing reliability problems. Also, when low-temperature metals are pressed against high-temperature metals (e.g., gold or aluminum contact pads, etc.), intermixing of metals does not reliably occur, resulting in low bond yield. For this reason, when using low-temperature metal bumps for flip-chip bonding, especially for chip-on-chip applications, bumps must be placed on both electronic parts (so that the contact is low-temperature-metal to low-temperature-metal) thereby increasing the likelihood of intermixing. But this disadvantageously increases fabrication cost.
Furthermore, low-temperature metals typically have a much lower thermal conductivity than high-temperature metals. For example, low temperature lead-indium solders have a thermal conductivity of about 0.22 watts per centimeter-Kelvin while high temperature silver has a thermal conductivity of about 4.2 W/cm-K. Consequently, low-temperature metals are not nearly as efficient for heat sinking flip-chip bonded devices.
And there is a fourth problem with using low-temperature metals for bumps. In particular, although it is possible to deposit low-temperature metal bumps that are small enough (i.e., have an area of about 10xc3x9710 microns and a height of 5-10 microns) for chip-on-chip applications, a contact pad of considerably larger size (e.g., 30xc3x9730 microns) is usually required since the bumps deform significantly during tacking. The larger size contact pads have a relatively large capacitance that results in relatively slower signal speeds. While slower signal speeds do not currently present a problem for many devices, this will become an issue as flip-chip bonding is used for high-speed devices.
For these reasons, a bump that is mechanically compliant, regardless of its metal composition, would benefit the art.
Some embodiments in accordance with the illustrative embodiment of the present invention provide a mechanically compliant bump that avoids some of the drawbacks of the prior art. In particular, such bumps are mechanically compliant even when they are formed of high-temperature metals.
A mechanically compliant bump in accordance with the illustrative embodiment of the invention includes a base, which is typically disposed on the contact pad of an electronics device. Depending from the periphery of an upper surface of the base is a wall that advantageously completely encircles the upper surface of the base. The wall is able to flex or deform under pressure, even when the wall is formed from high-temperature metal. The wall therefore provides mechanical compliance.
The mechanically compliant bump is tapered. That is, the width of the bump increases with increasing distance from the bottom surface of the base. The taper angle of the bump is in a range of about five to about thirty degrees.
In a method in accordance with the illustrative embodiment of the present invention, openings that are formed in a photoresist layer (for metal deposition) are reverse tapered. For the purposes of this specification, xe2x80x9creverse taper(ed),xe2x80x9d as that phrase is used to described openings in a photoresist layer, means that the openings are wider at the upper surface of the photoresist layer than at the lower surface thereof. This decrease in width (with increasing proximity to the lower surface of the photoresist) is the reverse of the taper applied to openings that are used in the prior art (to form flip-chip bumps), which increase in width (with increasing proximity to the lower surface of the photoresist).
As a consequence of the reverse taper of openings used in a method in accordance with the illustrative embodiment of the present invention, metal that is deposited in the openings deposits against the side-walls thereof, unlike the prior art. The deposited metal fills the lower half (approximately) of the opening, forming the base of the mechanically compliant bump. Above the base, the metal forms a thin wall adjacent to the side-wall of the opening.
Since mechanically compliant bumps in accordance with the illustrative embodiment of the present invention are compliant even when they are formed from high temperature metal, the use of low-temperature metal, and the accompanying drawbacks thereof, can be avoided.